AMD Details Renoir: The Ryzen Mobile 4000 Series 7nm APU Uncoveredby Dr. Ian Cutress on March 16, 2020 11:00 AM EST
Power and Battery Life
Earlier in the year AMD was keen to promote that in Renoir it has made significant advances as to how power is managed across the APU, leading to increased performance and better battery life. The two key figures here were ‘20% reduced SoC power’ and ‘5x reduction in power gating latency’ (also known as an 80% reduction, because you can’t have a 5x reduction of a time). We now have some details.
First up it should be mentioned that 7nm helps a lot here. The smaller process node, with smaller transistors (assuming they’ve been laid out correctly), will require a lower voltage. That lower voltage directly translates into lower power, and we’ve seen how well AMD has pushed the 7nm designs on the desktop and in the enterprise space to know that compared to previous process nodes, there is a lot of power to save here. That being said, the design choices and features matter too.
AMD’s power management all goes through a system-level management controller. For this generation, AMD has re-written the firmware with speed in mind (they claim 33% faster), but also made other improvements, such as aggressive clock gating of the L3 cache when not needed, and using power optimized circuits for IO features such as for the embedded display controller and PCIe physical layers.
The updated system management controller (SMC) is built around user preference. In this case if the user tells the OS he or she wants more performance, or more battery life, then the SMC can take into consideration everything involved in the system and plan accordingly. If the OS can provide guidance as to an upcoming workload, then voltages and frequencies (or parts of the chip unused can be put in idle), then the SMC is built to understand it.
Ultimately there are many sensors around the APU, monitoring activity and the type of activity going on in that particular region, even down to the types of instructions being used. The SoC is a lot more dynamic in its clock control, allowing for different clock domains in various parts of the SoC to be adjusted depending on both the activity of the region but also the thermal limits, system limits, and other items that might affect performance. This is especially useful for powering down parts of the SoC that are not in use, leading to AMD’s efficiency claims, or the performance claims such as maintaining a specific bandwidth across an interconnect (quality of service). The thresholds for these activity monitors can be set by the OS and by the user. The SMU also takes into account the power source (battery vs power supply) and connected hardware (displays, power over USB).
For the power gating latency, AMD has doubled the save and restore bus width from the buffers to the cores, allowing for a system to resume faster from a CPUOFF state. Not only this, but AMD is using the ACPI 6.3 specifications to take advantage of offering multiple C states in the OS.
One of the issues of the previous generation of Picasso APUs, on the left, is that there was only a single set of states that the processor could be in. This means that at any time, the CPU could fall from a power state (a P state) into a lower power state, or an idle state, or an off state. If the CPU went too far down this stack, while it would be saving power, each hop down the rabbit hole meant a longer time to get back out of it, diminishing performance and latency but also requiring more power changes at the silicon level. Each hop in its own right requires additional power.
With the new Renoir designs, a system can take advantage of multiple different sets of states. This means that the CPU can’t go down too low when the system is in use. With a system in use, the OS or system controller can’t put parts of the core into low power states because those are not available, which means that even if the system goes into the lowest power mode possible, while the system is still being used, then there are fewer jumps to get back up to high speed.
As the system becomes less used, known as ‘increased idle duration’, then the system has access to sets of states that allow the parts of the APU to enter deeper idle states. This means that the system can only enter a low frequency domain if that part of the core has been sufficiently idle, or user interaction has willed it.
This is all part of the ACPI 6.3 standard, and AMD states that this combined with the reduced SoC power gives both better battery life and better immediate performance for the user. To show this in action, AMD pinpointed a common activity that most users might be familiar with: opening applications.
In this case, AMD took the start of the PCMark 10 Application Loading benchmark. In this benchmark a number of applications are loaded, and the requirements are often more IO driven than CPU driven. A good CPU with a fast reaction time will keep its power and frequency low while the IO requests are being done, and speed up one or two threads when the CPU needs to get involved.
In AMD’s benchmark, where they are using frequency as a proxy for power, They show that in the initial 5 seconds of the test, the new Ryzen 4000 CPU is hovering at an idle frequency, whereas the older Ryzen 3000 CPU is fluttering around, even peaking near 4.0 GHz when it doesn’t need to. This allows parts of the new CPU to be powered down for longer periods of time, even when the system is actually in use.
When I asked AMD’s executives where they stand on battery life, one of them hinted that the difference between themselves and the competition (in similar designs) should be on the order of minutes rather than dozens of minutes. Specifically AMD sees itself better than the competition in productivity/web browsing workloads, graphics workloads, and video playback, and cited that most battery benchmarks don’t often take into account a good mix of ‘the average user’. A number of the media responded that often our benchmarks are geared towards different types of users consummate to our audience, such as gamers or content creators. Ultimately we will see what the results are when we have hardware on hand.
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uibo - Monday, March 16, 2020 - linkHTPC market insignificant
Samus - Tuesday, March 17, 2020 - linkI mean realistically there isn't anything a 10w Atom can't decode anymore...everything is overkill for HTPC.
As far as encoding, for what the general consumer does (twitch, etc) any midrange CPU can handle that in the background on top of any other tasks you demand. It won't be a 10-15w part, but certainly a 35w part.
R3MF - Tuesday, March 17, 2020 - linkeven AV1?
bearing in mind that a new htpc has a ~6 year life and AV1 is the future of streaming video.
close - Tuesday, March 17, 2020 - linkI have an X5-Z8350 Atom tablet at home, I will give it a run with an AV1 encoded full HD Youtube stream and see if it handles it reasonably. I would assume that a box with more adequate cooling would do even better.
PeachNCream - Tuesday, March 17, 2020 - linkHave to agree with this. HTPCs had a very brief glimmer of market presence a few years ago, but they never really took off or make a substantial enough splash. The population at large has little interest in adding the relative complexity of a computer to their media viewing experience and most home users are purchasing laptops, not even desktops, which are even less well-suited to acting as a fixed system attached to a large display panel. If AMD does grab that market, it will not be a measurable number of sales to say the least.
Spunjji - Tuesday, March 17, 2020 - linkI love my HTPC and am excited to rebuild it around Renoir, and I fully endorse the sentiment of this post. Most people get by with a Fire stick or the built-in "smart" features of your average modern TV.
PeachNCream - Tuesday, March 17, 2020 - linkIf I had time and was more interested in consuming video content, I would probably dive into building a HTPC as well, but it would be to appeal mainly to a desire to tinker. From a practical standpoint, I would be hard-pressed to find a credible amount of work for computer dedicated to that task because watching videos isn't something I do when I'm not on an exercise bike and my phone is good enough for that chore.
stephenbrooks - Tuesday, March 17, 2020 - linkLaptops make pretty good "HTPCs"... I plugged mine into a projector and sound system just today in fact
DanNeely - Monday, March 16, 2020 - linkFor power efficiency media en/decoding is normally done with fixed function hardware; doing it in software on the GPU's general purpose cores eats power like crazy. AV1 not being present means Renoir doesn't have a fixed function block - whether due to not being done yet, taking too much die area, or something else - but not being here means you're going to have to wait until the 5000 series APUs to get support in an AMD CPU.
Santoval - Tuesday, March 17, 2020 - linkBear in mind that this year will see the release of no less than *three* new video codecs. MPEG plan to release H.266/VVC (Versatile Video Coding), EVC (i.e Essential Video Coding) or MPEG-5 Part-1 and LCEVC (i.e. Low Complexity Enhancement Video Coding) or MPEG-5 Part-2. Each codec is targeted at a different market. For instance H.266/VVC is the direct successor of H.265/HEVC, while EVC is partly targeted against AV1 (its baseline profile, which is ~30% more bitrate efficient than H.264, will be royalty free).
LCEVC is not so much a new codec but a new technique to combine two layers of any two codecs at any resolution in a "hybrid" (stacked) way, in order to reduce computational complexity. Which works apparently. I place a link at the end of the comment which explains how that works. In other words the codec market of the next couple of years is going to quite more loaded and competitive than simply choosing between H.265, VP9 and AV1. This is something chip manufacturers will almost certainly take into account.
By the way, it is not yet fully clear if AV1 is going to be royalty free. Sisvel launched a patent pool for AV1 last year. Whether it has merit or not remains to be seen. However, patent confusion is worse than paying royalties for patents. If chip manufacturers have plans to add decoding and encoding support for VVC and EVC, for instance, they have already accounted the costs. But if they add AV1 support thinking it was patent free and then Sisvel goes to court to sue that would be a very unpleasant and unexpected surprise. Sisvel's patent claims are going to stall AV1 support unless they are resolved.