GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+by Anton Shilov on November 5, 2019 4:00 PM EST
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GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.
The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company’s RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries’ 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices GloFo's advanced fab technology.
GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.
For GlobalFoundries, it is important to land customers who need specialized process technologies and may not be ready for leading-edge processes from TSMC and Samsung Foundry for cost or other reasons. As for SiFive's involvement, this is a bit trickier – RISC-V itself isn't likely to be used for the core logic in deep learning accelerators, but it is a solid architecture to use for the embedded CPU cores needed to control the dataflows within an accelerator.
SiFive’s HBM2E interface and custom IP for GlobalFoundries’ 12LP and 12LP+ technology are being developed at GF’s Fab 8 in Malta, New York. The two companies expect that they'll be able to wrap up their work in the first half of 2020, at which point the IP will become available for licensing.
- GlobalFoundries Unveils 12LP+ Technology: Massive Performance & Power Improvements
- SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP
- Samsung Develops 12-Layer 3D TSV DRAM: Up to 24 GB HBM2
- Samsung HBM2E ‘Flashbolt’ Memory for GPUs: 16 GB Per Stack, 3.2 Gbps
- SK Hynix Announces 3.6 Gbps HBM2E Memory For 2020: 1.8 TB/sec For Next-Gen Accelerators
- SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
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Smell This - Wednesday, November 6, 2019 - linkMr Trout did not think this one out.
The 12LP+ FinFET process technology is a link in the chain -- or better yet, the incorporated interposers, dies, substrates, chiplets, cores, bumps, EBIBs and 'glue that binds all that stuff' together. GlobalFoundries (and SiFive) are comfortable enough to tap-out some chips in 2020 with 'edge computing looking to optimize for TOPS-per-milliwatt performance' for 'implementation primarily used for artificial intelligence training and inference'.
It ain't about 7nm, but it is about the design and IP that can bring new levels to HPC. Ian and Andrei have articles have articles about the challenges on the frontpage.
RISC-V 'U84 IP running internally on FPGA platforms' ? That sounds like high competition with Chipziilah's (and AMD's) hetro arch to me ...
HardwareDufus - Tuesday, November 5, 2019 - linkremember to that the process is relative now... actual size has been decoupled from the process naming for some time.... 7nm is not almost 1/2 of 12nm.... 12nm is more competitive against 7nm than you might think. Either way... I'm glad to see Malta get the work... They had a big layoff l when they announced they weren't pursuing 7nm..... Really affected the area.... lot of good paying jobs were lost.
Dragonstongue - Wednesday, November 6, 2019 - linkcheers to that, the workers need work, if this ensures more work (hopefully also as ecologically non wasteful as possible) the more the merrier...this leads to far more competition overall, which helps to push ever more GREATNESS to the industry (which is felt world wide)