Cortex A76 µarch - Frontend

Starting off with a rough overview of the Cortex A76 microarchitectural diagram we see the larger functional blocks. The A76 doesn’t look too different than other Arm processors in this regard and the differences come only with details that Arm is willing to divulge. To overly simplify it, this is a superscalar out-of-order core with a 4-wide decode front-end with 8 execution ports in the backend with a total implementation pipeline depth of 13 stages with the execution latencies of a 11 stage core.

In the front-end, Arm has created a new predict/fetch unit that it calls a “predict-directed fetch”, meaning the branch prediction unit feeds into the instruction fetch unit. This is a divergence from past Arm µarches and it allows for both higher performance and lower power consumption.

The branch prediction unit is what Arm calls a first in the industry in adopting a hybrid indirect predictor. The predictor is decoupled from the fetch unit and its supporting large structures operate separate from the rest of the machine – likely what this means is that it will be easier to clock-gate during operation to save on power. The branch predictor is supported by 3-level branch target caches; a 16-entry nanoBTB, a 64-entry microBTB and a 6000 entry main BTB. Arm claimed back in the A73 and A75 generations of branch predictors were able to nearly predict all taken branches so this new unit in the A76 seems to be one level above that in capability.

The branch unit operates at double the bandwidth of the fetch unit – it operates on 32B/cycle meaning up to 8 32b instructions per cycle. This feeds a fetch queue in front of the instruction fetch consisting of 12 “blocks”. The fetch unit operates at 16B/cycle meaning 4 32b instructions. The branch unit operating at double the throughput makes it possible to get ahead of the fetch unit. What this serves is that in the case of a mispredict it can hide branch bubbles in the pipeline and avoid stalling the fetch unit and the rest of the core. The core is said to able to cope with up to 8 misses on the I-side.

I mentioned at the beginning that the A76 is a 13-stage implementation with the latency of an 11-stage core. What happens is that in latency-critical paths the stages can be overlapped. One such cycle happens between the second cycle of the branch predict path and the first cycle of the fetch path. So effectively while there’s 4 (2+2) pipeline stages on the branch and fetch, the core has latencies of down to 3 cycles.

On the decode and rename stages we see a throughput of 4 instructions per cycle. The A73 and A75 were respectively 2 and 3-wide in their decode stages so the A76 is 33% wider than the last generation in this aspect. It was curious to see the A73 go down in decode width from the 3-wide A72, but this was done to optimise for power efficiency and “leanness” of the pipeline with goals of improving the utilisation of the front-end units. With the A76 going 4-wide, this is also Arms to date widest microarchitecture – although it’s still extremely lean when putting it into juxtaposition with competing µarches from Samsung or Apple.

The fetch unit feeds a decode queue of up to 16 32b instructions. The pipeline stages here consist of 2 cycles of instruction align and decode. It looks here Arm decided to go back to a 2-cycle decode as opposed to the 1-cycle unit found on the A73 and A75. As a reminder the Sophia cores still required a secondary cycle on the decode stage when handling instructions utilising the ASIMD/FP pipelines so Arm may have found other optimisation methods with the A76 µarch that warranted this design decision.

The decode stage takes in 4 instructions per cycle and outputs macro-ops at an average ratio of 1.06Mops per instruction. Entering the register rename stage we see heavy power optimisation as the rename units are separated and clock gated for integer/ASIMD/flag operations. The rename and dispatch are a 1 cycle stage which is a reduction from the 2-cycle rename/dispatch from the A73 and A75. Macro-ops are expanded into micro-ops at a ratio of 1.2µop per instruction and we see up to 8µops dispatched per cycle, which is an increase from the advertised 6µops/cycle on the A75 and 4µops/cycle on the A73.

The out-of-order window commit size of the A76 is 128 and the buffer is separated into two structures responsible for instruction management and register reclaim, called a hybrid commit system.  Arm here made it clear that it wasn’t focusing on increasing this aspect of the design as it found it as a terrible return on investment when it comes to performance. It is said that the performance scaling is 1/7th – meaning a 7% increase of the reorder buffer only results in a 1% increase in performance.  This comes at great juxtaposition compared to for example Samsung's M3 cores with a very large 224 ROB.

As a last note on the front-end, Arm said to have tried to optimised the front-end for lowest possible latency for hypervisor activity and system calls, but didn’t go into more details.

The Arm Cortex A76 - Introduction Cortex A76 µarch - Backend
Comments Locked


View All Comments

  • darwiniandude - Friday, June 1, 2018 - link

    Lots of Apple hate in these comments. Which is fine, nothing wrong with having your own opinion. Performance is important to me - I edit 4K (not for business purposes) from a few Fuji mirrorless bodies quite happily on iOS - on an iPhone X and iPad Pro. My fastest desktop and notebook machines I own currently are both Core2Duo. They simply cannot do it. I’m not a typical use case. I did have a quad i7, but I sold that machine (MacBook Pro) while I could still get a stupidly high amount of money back for it used. Don’t assume that no one on mobile wants high performance ARM cores - not everyone is just using Facebook messenger taking the occasional selfie all day.
    Also, I remember when AMD smoked Intel at times in the past. People argued, but there was never the “you don’t need that performance” type arguments.
  • leledumbo - Friday, June 1, 2018 - link

    That's what Apple is actually doing: single TDP configurable SoC for both their phones and pads (and tops if the rumor come true).

    The argument is not "you don't need that performance", but "most people don't need that performance". You are one of the few in the performance-needy pool. I know you exist, just not many, and that's what many manufacturers are aware of, so they don't take the Apple route.
  • hlovatt - Friday, June 1, 2018 - link

    But this is Anantech. We want the best. We want to push the envelope. I don’t want to read about ho hum performance at a good price. That’s for Consumer Reports or a myriad of other yawn sites.
  • serendip - Friday, June 1, 2018 - link

    4k editing on an iPad probably won't be using the CPU completely for processing though. There's a lot of stuff that can be passed on to faster and more efficient DSP and IP blocks. I've also run Quicksync encoding on Atom tablets running Windows, it's much faster than using the puny Atom cores directly.
  • darwiniandude - Saturday, June 2, 2018 - link Some discussion of performance on iPad at 4K. It really does work very well. Must be using the GPU also.
  • tipoo - Tuesday, September 4, 2018 - link

    Afaik, only playback will use dedicated blocks like Quicksync, editing itself, the rendering of new effects, would be heavily assisted by the GPU and partly on the CPU.
  • techconc - Tuesday, June 5, 2018 - link

    The "most people don't need that performance" argument may sound nice to say, but why do you think people buy new phones? They do it when their old phone feels slow,etc. A higher performing phone has a longer effective life span.

    Using phones as an example, Android has about 85% of the market share for devices sold. Yet, when Apple and Google report their active user base, Android barely maintains a 2:1 ratio over iOS devices. Why? The majority of Android devices sold are low end devices that have a much shorter effective life span.
  • Meteor2 - Monday, July 2, 2018 - link

    I kinda want to buy a new phone, but my Nexus 5X simply doesn't feel slow. So I haven't. And it must have less than half the performance of modern high-end phones.
  • Maxiking - Sunday, June 3, 2018 - link

    So another paper dragon, YAY.

    They promise the same every year, so statistically, if they keep repeating the lie every year, they will get there eventually!
  • Herkko - Wednesday, June 6, 2018 - link

    Tell me how much Nintendo Switch power and energy effiency grow if chance old ARM-cortex A57-A53 new ARM-cortex A76 CPU

Log in

Don't have an account? Sign up now